A current addition type D/A converter that converts a digital signal to an analog signal is known. The current addition type D/A converter determines a number of current source cells selected based on a digital signal and adds up output current values of the selected current source cells to output an analog signal.
FIG. 5 is a block diagram showing a configuration of the current addition type D/A converter. In FIG. 5, a digital signal Din is decoded by a decoder 110 to switch on and off switches SW1 through SWn. Each current output from current source cells 120 respectively is selected by on-state switches SW1 through SWn and added up to flow in a resistance R. A D/A converted analog signal is output as a voltage Aout at one end of the resistance R.
Next, the current source cells 120 are described. The current source cells 120 are composed of a plurality of current source cells each of which outputs a constant current. For example, a 10-bit D/A converter is composed of current source cells that correspond to 1,023 (210−1) LSBs (least significant bits) as shown in FIG. 6A. Output currents from these current source cells are selected by switches operated by an output of the decoder 110. In the decode method, a number of operating switches increases as a value of the binary code increases, which is called a thermometer code, too. In this case, although a linearity error is small, the number of switches SW1-SWn becomes as extremely large as 1,023, which makes implementation difficult.
Hence, the D/A converter is usually formed in such a way that lower-order and higher-order bits are expressed by binary and thermometer codes respectively. For example, when a 10-bit D/A converter is formed, as shown in FIG. 6B, current source cells are composed of 15 MSBs (most significant bits), 32 LSBs, 16 LSBs, 8 LSBs, 4 LSBs, 2 LSBs and 1 LSB, each of which is selected by the switches SW1-SWn operated by the output from the decoder 110, where each MSB corresponds to 64 LSBs. In this case, the number of the switches SW1-SWn is 21. Each current source cell with 64 LSBs, 32 LSBs, 16 LSBs, 8 LSBs, 4 LSBs, 2 LSBs or 1 LSB is composed of a constant current source such as a MOS transistor, whose W/L ratio increases with powers of 2.
A current addition type D/A converter as formed above is widely used, because it has merits such as high operating speed, small glitch, loose accuracy requirement for elements and easiness of CMOS fabrication.
From the viewpoint of conversion accuracy, it is ideal that the current addition type D/A converter outputs a constant current value from each of the current source cells that correspond to an MSB. However, in practice, the output current value from each current source cell is not constant, because there is a variation in transistor characteristics originated from the manufacturing process. Therefore, a differential linearity error or a non-linearity (integral linearity) error occurs during the D/A conversion. A magnitude of these errors depends on the variation of the output current from each current source cell.
Patent document 1, with an assumption that an error in the output current from each current source cell varies (linearly) with a certain inclination along the array direction, discloses a current source cell arrangement that cancels the variation to output a constant current. In the current source arrangement, as shown in FIG. 7, constant current sources MCELL1-MCELL15 are composed of a plurality of current source cells 100 that are arranged in matrix in which each of the current source cells 100 has a predetermined current value and a plurality (group) thereof are combined to provide each of the constant current sources MCELL1-MCELL15. The current source cell matrix is divided into an A-block 101 and a B-block 102 arranged symmetrically with respect to the center of the matrix. The constant current sources are formed by combining equal numbers of the current source cells in each block selected in a row or a column direction.
[Patent Document 1]
JP Patent Kokai Publication NO. JP-P2002-9247A (FIG. 1)